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| 512 K x 32 Static RAM SYS32512ZK/LK - 010/012/015 Issue 5.0 June 1999 Description The SYS32512 is a 512K x 8 SRAM module in a ZIP (ZK) or SIMM (LK & LKXA) packages with access times of 12 and 15ns, with 10ns parts under development. The device is available to commercial and industrial temperature grade. The LK SIMM package is designed for standard SIMM sockets. The LKXA is designed to fit both angled and standard sockets. Block Diagram A0~A18 /WE /OE 512K x 8 SRAM /CS1 512K x 8 D0~7 SRAM /CS2 512K x 8 D8~15 Features * Access times of 10, 12 and 15ns. * 5V + 10%. * Commercial and Industrial temperature grades * 72 pin ZIP and SIMM packages. * Industry standard footprint. * Power dissipation. * Operating Power (32 Bit) 4.62W (max) * Low power standby. (TTL) 1.32W (max) (CMOS) 330mW (max) * Completely Static Operation. /CS3 SRAM D16~23 512K x 8 SRAM /CS4 D24~D31 Pin Definition See page 2. Pin Functions Description Address Input Data Input/Output Chip Select Presence Detect Write Enable Output Enable No Connect Power Ground Signal A0~A18 D0~D31 /CS1~4 PD0~3 /WE /OE NC VCC VSS Package Details Plastic 72 Pin ZIP (ZK) Max. Dimensions (mm) - 97.80 x 20.61 x 5.90 Plastic 72 Pin SIMM (LK) Max. Dimensions (mm) - 108.08 x 15.00 x 5.25 Plastic 72 Pin SIMM (LKXA) Max. Dimensions (mm) - 108.08 x 20.32 x 4.55 Pin Definition - SYS32512 ZK/LK/LKXA Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Signal NC NC PD2 PD3 V SS PD0 PD1 D0 D8 D1 D9 D2 D10 D3 D11 V CC A0 A7 A1 A8 A2 A9 D12 D4 D13 D5 D14 D6 D15 D7 V SS /WE A15 A14 /CS2 /CS1 Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Signal /CS4 /CS3 A17 A16 /OE V SS D24 D16 D25 D17 D26 D18 D27 D19 A3 A10 A4 A11 A5 A12 V CC A13 A6 D20 D28 D21 D29 D22 D30 D23 D31 V SS A18 NC NC NC Note ZK : PD1=GND, PDO=PD2=PD3=OPEN PAGE 2 Issue 5.0 June 1999 Absolute Maximum Ratings(1) DC Operating Conditions Parameter Voltage on any pin relative to VSS Power Dissipation Storage Temperature Symbol VT PT TSTG (2) Min -0.3 to 4.0 -55 to Max +7.0 Unit V W +125 O C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability (2) VT can be -2.0V pulse of less than 2ns. Recommended Operating Conditions Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature (Commercial) (Industrial) Symbol VCC VIH VIL TA TAI Min 4.5 2.2 -0.3 0 -40 Typ 5.0 - Max 5.5 VCC+0.3 0.8 70 85 Unit V V V O O C C (I Suffix) DC Electrical Characteristics (VCC=5V+10%, TA=0OC to 70OC) Parameter Input Leakage Current Output Leakage Current Average Supply Current Standby Supply Current Address, /OE, /WE Worst Case 32 Bit TTL CMOS Symbol Test Condition ILI 0V < VIN < VCC Min -8 Typ - Max 8 Unit A A ILO /CS=VIH,VI/O=GND to VCC Min. Cycle, /CS=VIL, VIN =VIH or VIL, IOUT=OmA /CS=VIH /CS >VCC-0.2V, 0.2V >V IN>VCC-0.2V IOL=8.0mA IOH=-4.0mA -8 - 8 ICC1 ISB1 ISB2 V OL V OH 2.4 - 840 240 60 0.4 - mA mA mA V V Output Voltage Low Output Voltage High Notes (1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. (2) Typical Values are at VCC=5.0V, TA=25OC and specified loading. /CS above refers to /CS1~4 PAGE 3 Issue 5.0 June 1999 Capacitance (VCC = 5.0V, TA = 25OC) P aram eter Input C apacitan ce, (Address, /O E, /W E) Input C apacitan ce, (Other) O utpu t C apacita nce, 8 bit m ode (w orst case) S ym b ol C IN 1 C IN 2 C I/O T est C ondition V IN = 0V V IN = 0V V I/O = 0V M in T yp M ax 32 7 40 U nit pF pF pF Note : These Parameters are calculated not measured. Test Conditions * * * * * Input pulse levels : 0V to 3.0V Input rise and fall times : 3ns Input and Output timing reference levels : 1.5V Output Load : See Load Diagram. VCC = 5V+10% Output Load I/O Pin 166 1.76V 30pF Operation Truth Table /CS H L L L L /OE /WE X L H L H X H L L H Data Pins High Impedence Data Out Data In Data In High Impedence Supply Current ISB1,ISB2 ICC1 ICC1 ICC1 ISB1,ISB2 Mode Standby Read Write Write High Z Notes : H=VIH : L=VIL : X=VIH or VIL PAGE 4 Issue 5.0 June 1999 Read Cycle 10 Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold From Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z 12 15 AC Operating Conditions Symbol Min Max Min Max Min Max Units tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ 10 3 3 0 0 0 10 10 5 5 5 12 3 3 0 0 0 12 12 6 6 6 15 3 3 0 0 0 15 15 7 7 7 ns ns ns ns ns ns ns ns ns Write Cycle 10 Parameter Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold time from Write Time Output Active from End of Write Symbol tWC tCW tAW tAS tWP tWR tWHZ tDW tDH tOW 12 15 Units ns ns ns ns ns ns ns ns ns ns Min Max Min Max Min Max 10 7 7 0 7 0 0 5 0 3 5 12 8 8 0 8 0 0 6 0 3 6 15 10 10 0 10 0 0 7 0 3 10 - Under Development PAGE 5 Issue 5.0 June 1999 Read Cycle 1 (Address Controlled, /CS=/OE=VIL, /WE=VIH) tRC Address tOH Data Out Previous Data Valid tAA Data Valid Timing Waveforms Read Cycle 2 (/WE = VIH) tRC Address tAA tACS /CS tOHZ tOE /OE tOLZ tCLZ(4,5) Data Out Valid Data tOH tCHZ(3,4,5) NOTES(READ CYCLE) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL levels. 4. At any given temperature and voltage condition, t CHZ(Max.) is less than t CLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CS=V IL. 7. Address valid prior to coincident with /CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. /CS=/CS1~4 PAGE 6 Issue 5.0 June 1999 Write Cycle 1 (/OE = Clock) tWC Address tAW /OE tCW(3) /CS tWR(5) tAS(4) /WE tWP(2) tDW High Z Data In tOHZ(6) High Z(8) Data Out Valid Data tDH NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 ./CS=/CS1~4 PAGE 7 Issue 5.0 June 1999 Write Cycle 2 (/OE = Low Fixed) tWC Address tAW tCW(3) /CS tAS(4) /WE tDW High Z Data In tWHZ(6) High Z(8) Data Out Valid Data tOW (10) (9) tDH tWP(2) tWR(5) NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 ./CS=/CS1~4 PAGE 8 Issue 5.0 June 1999 Write Cycle 3 (/CS = Controlled) tWC Address tAW tCW(3) /CS tAS(4) /WE tDW High Z Data In tLZ High Z Data Out tWHZ(6) High Z(8) Valid Data tDH High Z tWP(2) tWR(5) NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. t WP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 /CS=/CS1~4 PAGE 9 Issue 5.0 June 1999 Package Details Plastic 72 pin ZIP (ZK) Front View 97.80 M ax. 5.90 Max. 16. 61 Ma x FROM S TA NDOF F 3.50 +0.5 Pin 1 6.35 Typ. 2.54 Typ. Pin 72 Plastic 72 pin SIMM (LK) Front View 108.08 Max. 1 5. 00 Max . L1 L2 5 . 2 5 Ma x . Pin 1 6.35 Typ. 1.27 Typ. Pin 72 Plastic 72 pin SIMM (LKXA) FRONT VIEW 108.08 MAX 4.55 MAX. L1 20.32 M A X Pin 1 6.35 typ 1.27 typ. Pin 72 PAGE 10 Issue 5.0 June 1999 Ordering Information Ordering Information SYS32512ZK/LK I - 010 Speed 010 = 10ns 012 = 12ns 015 = 15ns Blank = Commercial I = Industrial Power Consumption Package Blank = Standard ZK = Plastic 72 pin ZIP LK = Plastic 72 pin SIMM LKXA = Plastic 72 pin SIMM (Angled Sockets) 32512 = 512K x 32 SYS = SRAM Temperature Range Memory Organisation Technology Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. PAGE 11 http://www.mosaicsemi.com/ Issue 5.0 June 1999 |
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